After five decades of Moore's law the bottleneck hampering further downscaling of chip sizes is no longer process technology, but rather power consumption.
Leakage currents in present-day MOSFETs define the limit for the power-performance trade-off, i.e. limit clock rates for a given available power. A major component of these leakage currents is the subthreshold current, which sets a physical limit to how fast a transistor can be turned off: at most 1 order of magnitude current for a 60 mV change in gate bias.
To reduce dynamic power the chip's supply voltage may be scaled down as well, thereby causing an exponential increase in leakage current if the field-effect transistor's (FET) threshold voltage is to be scaled along. The resulting trade-off between power consumption and performance effectively follows from the impossibility to turn off transistors abruptly, as represented by a subthreshold slope of at least 60 mV per decade of current.
Proposed device architectures try to alleviate this limit of the subthreshold slope, often employing features of quantum mechanics to do so. However, there is still room for improvement in the design of these semiconductor devices.